1. Field of the Invention
The invention generally relates to polarity hold latches and, more particularly, to such a latch characterized by circuit simplicity, high speed and hazard free operation.
2. Description of the Prior Art
It has long been recognized that many benefits follow from successful efforts to eliminate unnecessary or redundant logic components from a given circuit. Redundant logic slows the speed of the machine in which it is used because each component introduces delay. Redundant logic increases the probability of component failure. Substantial cost savings can be realized in eliminating redundant logic, especially in applications where there is wide repetitive use of the simplified circuits.
Of course, circuit simplification should be achieved without compromising circuit stability or performance. In the case of the polarity hold latch, for example, efforts to reduce the number of logic components in an existing four-NAND gate latch must be cognizant of the need to substantially maintain the fast switching speed with which the latch can be set to the value of the input data line when the input control gate line is raised to a "1". In particular, techniques such as the addition of capacitive delay to avoid instability in the simplified circuit are undesirable because of the consequent worsened circuit response time. On the other hand, it is permissible to sacrifice an inconsequential performance characteristic, such as latch minimun reactivation interval, where the circuit application permits.